In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The Si-based microelectronic technology is currently faced with major materials challenges to achieve further miniaturization of integrated circuit devices. A gate stack containing a SiO2 gate dielectric layer and a degenerately doped polycrystalline Si gate electrode, which has served the industry for several decades, will be replaced with a gate stack having a higher capacitance.
High-capacitance materials, known as high-k materials (where “k” refers to the dielectric constant of the material), feature a dielectric constant greater than that of SiO2 (k˜3.9). In addition, high-k materials may refer to dielectric materials such as metallic silicates or oxides that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrates (e.g., SiO2, SiOxNy).
In addition to the gate dielectric layer, the gate electrode also represents a major challenge for future scaling of microelectronic devices. The introduction of metal-containing gate electrodes to replace the traditional doped poly-Si gate electrode can bring about several advantages. These advantages include elimination of the poly-Si gate depletion effect, reduction in sheet resistance, better reliability and potentially better thermal stability on the advanced high-k dielectric materials. In one example, switching from poly-Si to a metal-containing gate electrode can achieve a 2-3 Angstrom (Å) improvement in the effective or electrical thickness of the gate stack. This improvement occurs largely because the problem of poly-Si depletion at the interfaces with other materials is removed entirely.
Workfunction, resistivity, and compatibility with complementary metal oxide semiconductor (CMOS) technology are key parameters for the new gate electrode materials. Positive-channel Metal Oxide Semiconductor (PMOS) and the Negative-channel Metal Oxide Semiconductor (NMOS) transistor gate electrodes require different gate materials to achieve acceptable threshold voltages; the former having a Fermi level near the silicon valence band (E˜4 eV), and the latter having a Fermi level near the conduction band (E˜5.1 eV).
Conventional technology for controlling the work function of a gate electrode includes band-edge metal approach where a metal with a specific workfunction is selected; a P-metal (Re, Co, Ni, Ru, Pt, etc) with a workfunction greater than about 5 eV; and a N-metal (Ta, Hf, Y, La, Ir, etc) with a workfunction less than about 4.5 eV. However, the effective workfunction of a gate stack further depends on bulk and surface material properties, crystallographic orientation, and the permittivity of the high-k film interfacing with the gate electrode. In particular, interactions of the different materials at layer interfaces and diffusion of chemical species throughout a gate stack during post-processing, such as high temperature anneals, can affect the work function and other properties of the semiconductor device.
Recently, gate electrode metals and dielectric threshold voltage adjustment layers have been utilized to control the work function of gate stacks and to obtain the desired threshold voltages for N-MOS and P-MOS transistors in a manufactured semiconductor device. Exemplary threshold voltage adjustment layers include lanthanum oxide (La2O3) for N-MOS devices and aluminum oxide (Al2O3) for P-MOS devices. The dielectric threshold voltage adjustment layers have generally been positioned above the high-k gate dielectric and in contact with the gate electrode. It has been shown that during high temperature processing, elements in the dielectric threshold voltage adjustment layers generally diffuse through the high-k gate dielectric towards an interface layer (e.g., a high mobility, low defect SiO2 layer) positioned between the high-k gate dielectric and the substrate to cause threshold voltage adjustment near the interface of the high-k gate dielectric and the underlying interface layer. However, element(s) of some dielectric threshold voltage adjustment layers may not sufficiently diffuse through the high-k gate dielectric to fully adjust the threshold voltage of the semiconductor device to the desired value.
Thus, in view of the above-mentioned problems, new methods are needed for integrating metal-containing gate electrodes into gate stacks, and in particular, new methods are needed that allow for forming metal-containing gate electrodes with tunable workfunctions.